The present technique relates to an apparatus and method for performing a scalability check on a hardware description language (HDL) representation of a hardware circuit.
When designing hardware circuits, for example integrated circuits, it is known as an initial step to create a high-level representation of the hardware circuit in software form, using a hardware description language such as Verilog or VHDL. There are various levels of abstraction that can be used at this stage, but a common level of abstraction is the Register Transfer Level (RTL) abstraction, which can be used to represent a synchronous digital circuit in terms of registers and combinational logic, thus modelling the flow of digital signals between registers, along with the logical operations performed on those signals. The width of various signals can be expressed within the HDL representation of the circuit, and in some instances the width may be expressed in terms of at least one parameter, rather than being expressed as a constant value.
Whilst it is known to perform certain verification checks on the high-level representation of a digital circuit expressed in HDL form, those checks typically concentrate on checking that the HDL representation is syntactically correct. As part of the verification process, default values may be given to the various parameters specified within the HDL design. However, such verification processes cannot verify that the design will be scalable, i.e. whether if values of certain parameters are changed, the design will still operate as intended. It would accordingly be desirable to provide a mechanism that allowed for efficient and robust verification of the scalability of an HDL representation of a circuit.